1. Field of the Invention
The present invention relates in general to the generation of non-overlapping signals, and more particularly to a non-overlapping signal generation circuit in which an enable signal and a disable signal to be applied to an address signal decoder are generated in response to a pulse signal from an address transition detector, while accurately non-overlapping with each other.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a circuit diagram of a conventional non-overlapping signal generation circuit. As shown in this drawing, the conventional non-overlapping signal generation circuit comprises a NOR gate 10 for NORing a chip select signal /CS and an address signal Ai, a first inverter 20 for inverting an output signal from the NOR gate 10, a latch circuit 30 for latching the output signal from the NOR gate 10 and an output signal from the first inverter 20, a second inverter 40 for inverting a first output signal from the latch circuit 30, a third inverter 41 for inverting an output signal from the second inverter 40, and a fourth inverter 42 for inverting an output signal from the third inverter 41 and outputting the inverted signal as an enable signal AN to a decoder (not shown).
The conventional non-overlapping signal generation circuit further comprises a fifth inverter 43 for inverting a second output signal from the latch circuit 30, a sixth inverter 44 for inverting an output signal from the fifth inverter 43, a seventh inverter 45 for inverting an output signal from the sixth inverter 44 and outputting the inverted signal as a disable signal ANB to the decoder, and an address transition detector 50 for generating an address transition detect signal ATDN in response to the first and second output signals from the latch circuit 30.
The NOR gate 10 includes first and second PMOS transistors 11 and 12 and first and second NMOS transistors 13 and 14. The first PMOS transistor 11 has a gate for inputting the address signal Ai and a source for inputting a supply. voltage VCC. The second PMOS transistor 12 has a source connected to a drain of the first PMOS transistor 11 and a gate for inputting the chip select signal /CS. The first NMOS transistor 13 has a drain connected to a drain of the second PMOS transistor 12, a gate for inputting the address signal Ai and a source for inputting a ground voltage VSS. The second NMOS transistor 14 has a gate for inputting the chip select signal /CS, a source for inputting the ground voltage Vss and a drain connected to a first node N1. The first node N1 is connected in common to.sup.I the drains of the second PMOS transistor 12, first NMOS transistor 13 and second NMOS transistor 14 and an input terminal of the first inverter 20.
The latch circuit 30 includes first and second NAND gates 31 and 32. The first NAND gate 31 is adapted to NAND the output signal from the first inverter 20 and an output signal from the second NAND gate 32. The second NAND gate 32 is adapted to NAND the output signal from the NOR gate 10 and an output signal from the first NAND gate 31. A second node N2 is positioned between an output terminal of the first inverter 20 and one input terminal of the first NAND gate 31. A third node N3 is connected in common to an output terminal of the first NAND gate 31, an input terminal of the second inverter 40, one input terminal of the address transition detector 50 and one input terminal of the second NAND gate 32, the other input terminal of which is connected to the input terminal of the first inverter 20. A fourth node N4 is connected in common to an output terminal of the second NAND gate 32, the other input terminal of the first NAND gate 31, an input terminal of the fifth inverter 43 and the other input terminal of the address transition detector 50.
Noticeably, there may be provided non-overlapping signal generation circuits of the same number as that of address signal bits. For the convenience, the description will hereinafter be made with respect to only the non-overlapping signal generation circuit corresponding to one address signal bit Ai.
Now, the operation of, the conventional non-overlapping signal generation circuit with the above-mentioned construction will be described in detail with reference to FIGS. 2A to 2H.
First, when the chip select signal /CS is low in level, the non-overlapping signal generation circuit is selected. In this case, the second PMOS transistor 12 in the NOR gate 10 is turned on, whereas the second NMOS transistor 14 therein is turned off.
The operation of the conventional non-overlapping signal generation circuit will first be mentioned with respect to the case where the address signal Ai makes a low to high transition.
In the case where the address signal Ai goes from low to high in level as shown in FIG. 2A, the first PMOS transistor 11 in the NOR gate 10 is turned off, whereas the first NMOS transistor 13 therein is turned on. Because the second PMOS transistor 12 and the second NMOS transistor 14 in the NOR gate 10 were previously turned on and off, respectively, a signal on the first node N1 goes from high to low in level as shown in FIG. 2B.
The first inverter 20 inverts the signal on the first node N1 from low to high in level and outputs the resultant signal as shown in FIG. 2C to the second node N2. The high level signal on the second node N2 is applied to the one input terminal of the first NAND gate 31 in the latch circuit 30. As a result, a signal level on the third node N3 is determined depending on that at the other input terminal of the first NAND gate 31.
The low level signal on the first node N1 is applied to the other input terminal of the second NAND gate 32 in the latch circuit 30. As a result, the second NAND gate 32 outputs a low to high transition signal as shown in FIG. 2E to the fourth node N4 regardless of a signal level at its one input terminal. The high level signal on the fourth node N4 is applied to the other input terminal of the first NAND gate 31.
Subsequently, the signal on the third node N3 goes from high to low in level as shown in FIG. 2D.
In result, the signal on the third node N3 makes the transition later than that on the fourth node N4 by a delay time of the second NAND gate 32.
The signal on the fourth node N4 is sequentially inverted by the fifth to seventh inverters 43-45 and applied to the decoder as the disable signal ANB which goes from high to low in level as shown in FIG. 2G.
Then, the signal on the third node N3 is sequentially inverted by the second to fourth inverters 40-42 and applied to the decoder as the enable signal AN which goes from low to high in level as shown in FIG. 2F. The enable signal AN makes the transition later than the disable signal ANB by the delay time of the second NAND gate 32.
Therefore, the enable signal AN and the disable signal ANB are applied to the decoder, with their high levels non-overlapping with each other by the delay time of the second NAND gate 32.
In response to the signals on the third and fourth nodes N3 and N4, the address transition detector 50 generates the address transition detect signal ATDN which is a high level pulse signal as shown in FIG. 2H.
Next, the operation of the conventional non-overlapping signal generation circuit will be mentioned with respect to the case where the address signal Ai makes a high to low transition.
In the case where the address signal Ai goes from high to low in level as shown in FIG. 2A, the first PMOS transistor 11 in the NOR gate 10 is turned on, whereas the first NMOS transistor 13 therein is turned off. Because the second PMOS transistor 12 and the second NMOS transistor 14 in the NOR gate 10 were previously turned on and off, respectively, the signal on the first node N1 goes from low to high in level as shown in FIG. 2B.
The first inverter 20 inverts the signal on the first node N1 from high to low in level and outputs the resultant signal as shown in FIG. 2C to the second node N2.
The low level signal on the second node N2 is applied to the one input terminal of the first NAND gate 31 in the latch circuit 30. As a result, the first NAND gate 31 outputs a low to high transition signal as shown in FIG. 2D to the third node N3 regardless of a signal level at its other input terminal.
Subsequently, the signal on the fourth node N4 goes from high to low in level as shown in FIG. 2E in response to the high level signal on the third node N3 and the high level signal on the first node N1.
In result, the signal on the fourth node N4 makes the transition later than that on the third node N3 by a delay time of the first NAND gate 31.
The signal on the third node N3 is sequentially inverted by the second to fourth inverters 40-42 and applied to the decoder as the enable signal AN which goes from high to low in level as shown in FIG. 2F.
Then, the signal on the fourth node N4 is sequentially inverted by the fifth to seventh inverters 43-45 and applied to the decoder as the disable signal ANB which goes from low to high in level as shown in FIG. 2G. The disable signal ANB makes the transition later than the enable signal AN by the delay time of the first NAND gate 31.
Therefore, the enable signal AN and the disable signal ANB are applied to the decoder, with their high levels non-overlapping with each other by the delay time of the first NAND gate 31.
In response to the signals on the third and fourth nodes N3 and N4, the address transition detector 50 generates the address transition detect signal ATDN which is the high level pulse signal as shown in FIG. 2H.
However, the above-mentioned conventional non-overlapping signal generation circuit has a disadvantage in that the delay times of the NAND gates are not constant due to variations in input voltages and temperatures of transistors us&d in the NAND gates. For this reason, the enable signal and the disable signal cannot be generated with their high levels accurately non-overlapping with each other. In order to solve such a problem, the transistors may be optimized in size by the user. Unfortunately, it is actually difficult to optimize the transistor size.